FPGA Verilog 实现 3-8译码器

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3-8 译码器说明

有3个开关， 按下任意个开关，输出 0~8号灯

.ucf 配置文件

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.ucf 配置文件
NET "ext_clk_25m"   LOC = P23 | IOSTANDARD = LVCMOS33;
NET "ext_rst_n"     LOC = P24 | IOSTANDARD = LVCMOS33;
NET "led[0]"        LOC=P17   | IOSTANDARD = LVCMOS33;
NET "led[1]"        LOC=P16   | IOSTANDARD = LVCMOS33;
NET "led[2]"        LOC=P15   | IOSTANDARD = LVCMOS33;
NET "led[3]"        LOC=P14   | IOSTANDARD = LVCMOS33;
NET "led[4]"        LOC=P12   | IOSTANDARD = LVCMOS33;
NET "led[5]"        LOC=P11   | IOSTANDARD = LVCMOS33;
NET "led[6]"        LOC=P10   | IOSTANDARD = LVCMOS33;
NET "led[7]"        LOC=P9    | IOSTANDARD = LVCMOS33;
NET "switch[0]"     LOC=P29   | IOSTANDARD = LVCMOS33;
NET "switch[1]"     LOC=P30   | IOSTANDARD = LVCMOS33;
NET "switch[2]"     LOC=P32   | IOSTANDARD = LVCMOS33;

.v 文件

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.v 文件
module sp6(
    input ext_clk_25m, //外部输入25MHz时钟信号
    input ext_rst_n, //外部输入复位信号，低电平有效
    input[3:0] switch, //4个拨码开关接口，ON -- 低电平；OFF -- 高电平
    output reg[7:0] led  //8个LED指示灯接口
  );

always @ (posedge ext_clk_25m or negedge ext_rst_n)
    if(!ext_rst_n) led <= 8'hff;     //所有LED关闭
    else
    begin
        case(switch[2:0])
            3'b111: led <= 8'b1111_1111; //亮灯表示 0
            3'b110: led <= 8'b1111_1110; //亮灯表示 1
            3'b101: led <= 8'b1111_1101; //亮灯表示 2
            3'b100: led <= 8'b1111_1011; //亮灯表示 3
            3'b011: led <= 8'b1111_0111; //亮灯表示 4
            3'b010: led <= 8'b1110_1111; //亮灯表示 5
            3'b001: led <= 8'b1101_1111; //亮灯表示 6
            3'b000: led <= 8'b1011_1111; //亮灯表示 7
    endcase
 end

endmodule